A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low- Power Application in 90nm CMOS

Ultra-low power device is very popular in recent years because of some applications like medical device and communications. For the ultralow-power consideration, the crucial in SRAMs are stability and reliability. In conventional 6T SRAMs is hard to achieve reliability in sub-threshold operation. Hence, some researchers have considered different configuration SRAMs cell for sub-threshold operations having single-ended 8T, 9T, 10T or differential pair structure for improved stability and reliability. In this paper, the purposed 10T differential bit-cell that effectively separates read and write operation path, therefore achieving high stability. The purposed 1kb 10T sub-threshold SRAM (64x16) implemented in 90nm CMOS technology operates at 10MHz at 300mV with measured power consumption of 1.48μW and energy consumption of 0.296pJ for one write and one read operation.